1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly, to fabricating a test structure that may be used to determine the optimum length of lightly doped drains ("LDDs") employed by a transistor, wherein the test structure contains varying LDD lengths for transistors having the same gate length.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline ("polysilicon") material over a relatively thin gate oxide. The polysilicon material and gate oxide is then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant material. If the impurity dopant material used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant material is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device.
Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. The methods by which n-channel devices and p-channel devices are formed entail unique problems associated with each device. As layout densities increase, the problems are exacerbated. N-channel devices are particularly sensitive to so-called short-channel effects ("SCE"). The distance between a source-side junction and a drain-side junction is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length ("Leff"). In VLSI designs, as the physical channel becomes small, so too must the Leff. SCE becomes a predominant problem whenever Leff drops below approximately 1.0 .mu.m
A problem related to SCE and the subthreshold currents associated therewith, but altogether different, is the problem of hot-carrier effects ("HCE"). HCE is a phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. The electric field at the drain primarily causes electrons in the channel to gain kinetic energy and become "hot". As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome the problems of sub-threshold current and threshold shift resulting from SCE and HCI, an alternative drain structure known as lightly doped drain ("LDD") is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce Em. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section within the junction at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. The second implant dose is the source/drain implant placed within the junction laterally outside the LDD area. Resulting from the first and second implants, a dopant gradient (i.e., "graded junction") occurs at the interface between the source and channel as well as between the drain and channel.
Unfortunately, the addition of an LDD implant adjacent the channel adds capacitance and resistance to the source/drain pathway. This added resistance, generally known as parasitic resistance, can have many deleterious effects. First, parasitic resistance can decrease the saturation current (i.e., current above threshold). Second, parasitic capacitance can decrease the overall speed of the transistor. The deleterious effects of decreased saturation current and transistor speed is best explained in reference to a transistor having conventional source and drain LDDs. Using an n-channel example, the drain resistance R.sub.D causes the gate edge near the drain to "see" a voltage, e.g., less than VDD, to which the drain is typically connected. Similarly, the source resistance R.sub.S causes the gate edge near the source to see some voltage, e.g., more than ground. The drive current along the source-drain path depends mostly on the voltage applied between the gate and source, i.e., V.sub.GS. If V.sub.GS exceeds the threshold amount, the transistor will go into saturation according to the following relation: EQU I.sub.DSAT =K/2*(V.sub.GS -V.sub.T).sup.2
where I.sub.DSAT is saturation current, K is a value derived as a function of the process parameters used in producing the transistor, and V.sub.T is the threshold voltage. Reducing or eliminating R.sub.S would therefore draw the source-coupled voltage closer to ground and thereby increase the effective V.sub.GS. From the above equation, it can be seen that increasing V.sub.GS directly increases I.sub.DSAT. While it would seem beneficial to decrease R.sub.D as well, R.sub.D is nonetheless needed to maintain HCI control. Accordingly, a substantial LDD area is required in the drain area.
Proper LDD design must take into account the need for minimizing parasitic resistance R.sub.S at the source side while at the same time attenuating Em at the drain side of the channel. A well engineered LDD design is necessary to reduce HCI and SCE and to maximize the saturation current of a transistor. It is therefore desirable to derive a transistor test structure that provides for determining the optimum LDD length of a transistor. The thickness of the sidewall spacers employed by a transistor controls the length of the LDDs. Thus, it is important to analyze the effect that varying spacer thickness has on the performance of a transistor. If the spacer is too small, then the corresponding, shortened LDD length might not sufficiently suppress HCI and SCE. Yet, if the spacer width and corresponding LDD length is too large, then parasitic resistance R.sub.S may unduly jeopardize transistor operation. A test structure which can determine optimal LDD length for various processes would greatly enhance the chosen process and/or transistor operation.